p16f877x.inc
Register definitions for PIC16F877 processor (using variables with fixed addresses).
// REGISTER FILES
char _INDF@0x00;
char _TMR0@0x01;
char _PCL@0x02;
char _STATUS@0x03;
char _FSR@0x04;
char _PORTA@0x05;
char _PORTB@0x06;
char _PORTC@0x07;
char _PORTD@0x08;
char _PORTE@0x09;
char _PCLATH@0x0A;
char _INTCON@0x0B;
char _PIR1@0x0C;
char _PIR2@0x0D;
char _TMR1L@0x0E;
char _TMR1H@0x0F;
char _T1CON@0x10;
char _TMR2@0x11;
char _T2CON@0x12;
char _SSPBUF@0x13;
char _SSPCON@0x14;
char _CCPR1L@0x15;
char _CCPR1H@0x16;
char _CCP1CON@0x17;
char _RCSTA@0x18;
char _TXREG@0x19;
char _RCREG@0x1A;
char _CCPR2L@0x1B;
char _CCPR2H@0x1C;
char _CCP2CON@0x1D;
char _ADRESH@0x1E;
char _ADCON0@0x1F;
char _OPTION_REG@0x81;
char _TRISA@0x85;
char _TRISB@0x86;
char _TRISC@0x87;
char _TRISD@0x88;
char _TRISE@0x89;
char _PIE1@0x8C;
char _PIE2@0x8D;
char _PCON@0x8E;
char _SSPCON2@0x91;
char _PR2@0x92;
char _SSPADD@0x93;
char _SSPSTAT@0x94;
char _TXSTA@0x98;
char _SPBRG@0x99;
char _ADRESL@0x9E;
char _ADCON1@0x9F;
char _EEDATA@0x10C;
char _EEADR@0x10D;
char _EEDATH@0x10E;
char _EEADRH@0x10F;
char _EECON1@0x18C;
char _EECON2@0x18D;
// STATUS Bits Masks
#define _IRP 0x80
#define _RP1 0x40
#define _RP0 0x20
#define _NOT_TO 0x10
#define _NOT_PD 0x08
#define _Z 0x04
#define _DC 0x02
#define _C 0x01
// INTCON Bits Masks
#define _GIE 0x80
#define _PEIE 0x40
#define _T0IE 0x20
#define _INTE 0x10
#define _RBIE 0x08
#define _T0IF 0x04
#define _INTF 0x02
#define _RBIF 0x01
// PIR1 Bits Masks
#define _PSPIF 0x80
#define _ADIF 0x40
#define _RCIF 0x20
#define _TXIF 0x10
#define _SSPIF 0x08
#define _CCP1IF 0x04
#define _TMR2IF 0x02
#define _TMR1IF 0x01
// PIR2 Bits Masks
#define _EEIF 0x10
#define _BCLIF 0x08
#define _CCP2IF 0x01
// T1CON Bits Masks
#define _T1CKPS1 0x20
#define _T1CKPS0 0x10
#define _T1OSCEN 0x08
#define _NOT_T1SYNC 0x04
#define _T1INSYNC 0x04 // Backward compatibility only
#define _T1SYNC 0x04
#define _TMR1CS 0x02
#define _TMR1ON 0x01
// T2CON Bits Masks
#define _TOUTPS3 0x40
#define _TOUTPS2 0x20
#define _TOUTPS1 0x10
#define _TOUTPS0 0x08
#define _TMR2ON 0x04
#define _T2CKPS1 0x02
#define _T2CKPS0 0x01
// SSPCON Bits Masks
#define _WCOL 0x80
#define _SSPOV 0x40
#define _SSPEN 0x20
#define _CKP 0x10
#define _SSPM3 0x08
#define _SSPM2 0x04
#define _SSPM1 0x02
#define _SSPM0 0x01
// CCP1CON Bits Masks
#define _CCP1X 0x20
#define _CCP1Y 0x10
#define _CCP1M3 0x08
#define _CCP1M2 0x04
#define _CCP1M1 0x02
#define _CCP1M0 0x01
// RCSTA Bits Masks
#define _SPEN 0x80
#define _RX9 0x40
#define _RC9 0x40 // Backward compatibility only
#define _NOT_RC8 0x40 // Backward compatibility only
#define _RC8_9 0x40 // Backward compatibility only
#define _SREN 0x20
#define _CREN 0x10
#define _ADDEN 0x08
#define _FERR 0x04
#define _OERR 0x02
#define _RX9D 0x01
#define _RCD8 0x01 // Backward compatibility only
// CCP2CON Bits Masks
#define _CCP2X 0x20
#define _CCP2Y 0x10
#define _CCP2M3 0x08
#define _CCP2M2 0x04
#define _CCP2M1 0x02
#define _CCP2M0 0x01
// ADCON0 Bits Masks
#define _ADCS1 0x80
#define _ADCS0 0x40
#define _CHS2 0x20
#define _CHS1 0x10
#define _CHS0 0x08
#define _GO 0x04
#define _NOT_DONE 0x04
#define _GO_DONE 0x04
#define _ADON 0x01
// OPTION_REG Bits Masks
#define _NOT_RBPU 0x80
#define _INTEDG 0x40
#define _T0CS 0x20
#define _T0SE 0x10
#define _PSA 0x08
#define _PS2 0x04
#define _PS1 0x02
#define _PS0 0x01
// TRISE Bits Masks
#define _IBF 0x80
#define _OBF 0x40
#define _IBOV 0x20
#define _PSPMODE 0x10
#define _TRISE2 0x04
#define _TRISE1 0x02
#define _TRISE0 0x01
// PIE1 Bits Masks
#define _PSPIE 0x80
#define _ADIE 0x40
#define _RCIE 0x20
#define _TXIE 0x10
#define _SSPIE 0x08
#define _CCP1IE 0x04
#define _TMR2IE 0x02
#define _TMR1IE 0x01
// PIE2 Bits Masks
#define _EEIE 0x10
#define _BCLIE 0x08
#define _CCP2IE 0x01
// PCON Bits Masks
#define _NOT_POR 0x02
#define _NOT_BO 0x01
#define _NOT_BOR 0x01
// SSPCON2 Bits Masks
#define _GCEN 0x80
#define _ACKSTAT 0x40
#define _ACKDT 0x20
#define _ACKEN 0x10
#define _RCEN 0x08
#define _PEN 0x04
#define _RSEN 0x02
#define _SEN 0x01
// SSPSTAT Bits Masks
#define _SMP 0x80
#define _CKE 0x40
#define _D 0x20
#define _I2C_DATA 0x20
#define _NOT_A 0x20
#define _NOT_ADDRESS 0x20
#define _D_A 0x20
#define _DATA_ADDRESS 0x20
#define _P 0x10
#define _I2C_STOP 0x10
#define _S 0x08
#define _I2C_START 0x08
#define _R 0x04
#define _I2C_READ 0x04
#define _NOT_W 0x04
#define _NOT_WRITE 0x04
#define _R_W 0x04
#define _READ_WRITE 0x04
#define _UA 0x02
#define _BF 0x01
// TXSTA Bits Masks
#define _CSRC 0x80
#define _TX9 0x40
#define _NOT_TX8 0x40 // Backward compatibility only
#define _TX8_9 0x40 // Backward compatibility only
#define _TXEN 0x20
#define _SYNC 0x10
#define _BRGH 0x04
#define _TRMT 0x02
#define _TX9D 0x01
#define _TXD8 0x01 // Backward compatibility only
// ADCON1 Bits Masks
#define _ADFM 0x80
#define _PCFG3 0x08
#define _PCFG2 0x04
#define _PCFG1 0x02
#define _PCFG0 0x01
// EECON1 Bits Masks
#define _EEPGD 0x80
#define _WRERR 0x08
#define _WREN 0x04
#define _WR 0x02
#define _RD 0x01
Copyright© 2002 Pavel Baranov